`timescale 1ns / 1ps



module dlatch(Q,QN,D,RST,EN);
    output reg Q,QN;
    input D;
    input EN,RST;
    always@(D,RST,EN)begin
        if(RST)begin
                Q =0; QN  =1;
        end
        else if(EN)begin
            Q<=D;QN<=~D;
            end
        end
    
endmodule
